MCS6500 Programming Manual

MCS6500
Microcomputer Family
Programming Manual


APPENDIX B

INSTRUCTION LIST

ALPHABETIC BY MNEMONIC

WITH OP CODES, EXECUTION CYCLES

AND MEMORY REQUIREMENTS

The following notation applies to this summary:

           A              Accumulator
           X, Y           Index Registers
           M              Memory
           P              Processor Status Register
           S              Stack Pointer
           ✓              Change
           _              No Change
           +              Add
           ∧              Logical AND
           -              Subtract
           ∨              Logical Exclusive Or
           ↑              Transfer from Stack
           ↓              Transfer to Stack
           →              Transfer to
           ←              Transfer to
           ∨              Logical OR
           PC             Program Counter
           PCH            Program Counter High
           PCL            Program Counter Low
           OPER           OPERAND
           #              IMMEDIATE ADDRESSING MODE

Note: At the top of each table is located in parentheses a
reference number (Ref: XX) which directs the user to
that Section in the MCS6500 Microcomputer Family
Programming Manual in which the instruction is defined
and discussed.

ADC Add memory to accumulator with carry

Operation: A + M + C → A, C                              N Z C I D V
                                                        ✓ ✓ ✓ - - ✓
                   (Ref: 2.2.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   ADC # Oper
 ADC   Oper
 ADC   Oper, X
 ADC   Oper
 ADC   Oper, X
 ADC   Oper, Y
 ADC   (Oper, X)
 ADC   (Oper), Y
    69
  65
  75
  6D
  7D
  79
  61
  71
     2
   2
   2
   3
   3
   3
   2
   2
     2
   3
   4
   4
   4*
   4*
   6
   5*

*  Add 1 if page boundary is crossed.

AND "AND" memory with accumulator
Logical AND to the accumulator

Operation: A ∧ M → A                                     N Z C I D V
                                                        ✓ ✓ ✓ - - ✓
                   (Ref: 2.2.3.0)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   AND # Oper
 AND   Oper
 AND   Oper, X
 AND   Oper
 AND   Oper, X
 AND   Oper, Y
 AND   (Oper, X)
 AND   (Oper), Y
    29
  25
  35
  2D
  3D
  39
  21
  31
     2
   2
   2
   3
   3
   3
   2
   2
     2
   3
   4
   4
   4*
   4*
   6
   5*

*  Add 1 if page boundary is crossed.

ASL ASL Shift Left One Bit (Memory or Accumulator)
               ┌─┬─┬─┬─┬─┬─┬─┬─┐
Operation: C ← │7│6│5│4│3│2│1│0│ ← 0                     N Z C I D V
               └─┴─┴─┴─┴─┴─┴─┴─┘                        ✓ ✓ ✓ - - -
                   (Ref: 2.2.3.0)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Accumulator
 Zero Page
 Zero Page, X  
 Absolute
 Absolute, X
   ASL   A
 ASL   Oper
 ASL   Oper, X
 ASL   Oper
 ASL   Oper, X
    0A
  06
  16
  0E
  1E
     1
   2
   2
   3
   3
     2
   5
   6
   6
   7


BCC Branch on Carry Clear

Operation: Branch on C = 0                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.3)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BCC   Oper
    90
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.

BCS Branch on Carry Set

Operation: Branch on C = 1                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.4)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BCS   Oper
    B0
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.

BEQ Branch on result zero

Operation: Branch on Z = 1                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.5)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BEQ   Oper
    F0
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.

BIT Test bits in memory with accumulator

Operation: A ∧ M, M₇ → N, M₆ → V

  Bit 6 and 7 are transferred to the status register.    N Z C I D V  
  If the result of A ∧ M is zero then Z = 1, otherwise   - - - - - -
  Z = 0
                   (Ref: 4.2.1.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Zero Page 
   BIT   Oper
  24
  2
    3
   Absolute
   BIT   Oper
  2C
  3
    4


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.


BMI Branch on result minus

Operation: Branch on N = 1                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.1)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BMI   Oper
    30
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.

BNE Branch on result not zero

Operation: Branch on Z = 0                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.6)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BNE   Oper
    D0
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.

BPL Branch on result plus

Operation: Branch on N = 0                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.2)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BPL   Oper
    10
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.

BRK Force Break

Operation: Forced Interrupt PC + 2 ↓ P ↓                 N Z C I D V
                                                         - - - 1 - -
                     (Ref: 9.11)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   BRK
    00
     1
     7*


1. A BRK command cannot be masked by setting I.

BVC Branch on overflow clear

Operation: Branch on V = 0                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.8)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BVC   Oper
    50
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.

BVS Branch on overflow set

Operation: Branch on V = 1                               N Z C I D V
                                                         - - - - - -
                   (Ref: 4.1.1.7)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Relative
   BVS   Oper
    70
     2
     2*


*  Add 1 if branch occurs to same page.
*  Add 2 if branch occurs to different page.


CLC Clear carry flag

Operation: 0 → C                                         N Z C I D V
                                                         - - 0 - - -
                     (Ref: 3.0.2)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   CLC
    18
     1
     2


CLD Clear decimal mode

Operation: 0 → D                                         N Z C I D V
                                                         - - - - 0 -
                     (Ref: 3.0.2)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   CLD
    D8
     1
     2


CLI Clear interrupt disable bit

Operation: 0 → I                                         N Z C I D V
                                                         - - - 0 - -
                     (Ref: 3.0.2)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   CLI
    58
     1
     2


CLV Clear overflow flag

Operation: 0 → V                                         N Z C I D V
                                                         - - - - - 0
                     (Ref: 3.6.1)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   CLV
    B8
     1
     2


CMP Compare memory and accumulator

Operation: A - M                                         N Z C I D V
                                                        ✓ ✓ ✓ - - -
                   (Ref: 4.2.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   CMP # Oper
 CMP   Oper
 CMP   Oper, X
 CMP   Oper
 CMP   Oper, X
 CMP   Oper, Y
 CMP   (Oper, X)
 CMP   (Oper), Y
    C9
  C5
  D5
  CD
  DD
  D9
  C1
  D1
     2
   2
   2
   3
   3
   3
   2
   2
     2
   3
   4
   4
   4*
   4*
   6
   5*

*  Add 1 if page boundary is crossed.

CPX Compare Memory and Index X

Operation: X - M                                         N Z C I D V
                                                        ✓ ✓ ✓ - - -
                     (Ref: 7.8)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Absolute
   CPX # Oper
 CPX   Oper
 CPX   Oper
    E0
  E4
  EC
     2
   2
   3
     2
   3
   4

    
CPY Compare Memory and Index Y

Operation: Y - M                                         N Z C I D V
                                                        ✓ ✓ ✓ - - -
                     (Ref: 7.9)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Absolute
   CPY # Oper
 CPY   Oper
 CPY   Oper
    C0
  C4
  CC
     2
   2
   3
     2
   3
   4


DEC Decrement memory by one

Operation: M - 1 → M                                     N Z C I D V
                                                        ✓ ✓ - - - -
                    (Ref: 10.7)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Zero Page
 Zero Page, X 
 Absolute
 Absolute, X
   DEC # Oper
 DEC   Oper
 DEC   Oper, X
 DEC   Oper
    C6
  D6
  CE
  DE
     2
   2
   3
   3
     5
   6
   6
   7


DEX Decrement Index X by one

Operation: X - 1 → X                                     N Z C I D V
                                                        ✓ ✓ - - - -
                    (Ref: 7.6)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   DEX
    CA
     1
     2


DEY Decrement Index Y by one

Operation: Y - 1 → Y                                     N Z C I D V
                                                        ✓ ✓ - - - -
                    (Ref: 7.7)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   DEY
    88
     1
     2


EOR "Exclusive-Or" memory with accumulator

Operation: A ∨ M → A                                     N Z C I D V
                                                        ✓ ✓ - - - -
                   (Ref: 4.2.1.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   EOR # Oper
 EOR   Oper
 EOR   Oper, X
 EOR   Oper
 EOR   Oper, X
 EOR   Oper, Y
 EOR   (Oper, X)
 EOR   (Oper), Y
    49
  45
  55
  4D
  5D
  59
  41
  51
     2
   2
   2
   3
   3
   3
   2
   2
     2
   3
   4
   4
   4*
   4*
   6
   5*

*  Add 1 if page boundary is crossed.

INC Increment memory by one

Operation: M + 1 → M                                     N Z C I D V
                                                        ✓ ✓ - - - -
                    (Ref: 10.6)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Zero Page
 Zero Page, X 
 Absolute
 Absolute, X
   INC # Oper
 INC   Oper
 INC   Oper, X
 INC   Oper
    E6
  F6
  EE
  FE
     2
   2
   3
   3
     5
   6
   6
   7


INX Increment Index X by one

Operation: X + 1 → X                                     N Z C I D V
                                                        ✓ ✓ - - - -
                     (Ref: 7.4)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   INX
    E8
     1
     2


INY Increment Index Y by one

Operation: Y + 1 → Y                                     N Z C I D V
                                                        ✓ ✓ - - - -
                     (Ref: 7.5)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   INY
    C8
     1
     2


JMP Jump to new location

Operation: (PC + 1) → PCL                                N Z C I D V
           (PC + 2) → PCH                                - - - - - -
                     (Ref: 4.0.2)
                     (Ref: 9.8.1)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Absolute
 Indirect
   JMP Oper
 JMP (Oper)
    4C
  6C
     3
   3
     3
   5


JSR Jump to new location saving return address

Operation: (PC + 1) → PCL                                N Z C I D V
           (PC + 2) → PCH                                - - - - - -
                     (Ref: 4.0.2)
                     (Ref: 9.8.1)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Absolute
 Indirect
   JMP Oper
 JMP (Oper)
    4C
  6C
     3
   3
     3
   5


LDA Load accumulator with memory

Operation: M → A                                         N Z C I D V
                                                        ✓ ✓ - - - -
                     (Ref: 2.1.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   LDA # Oper
 LDA   Oper
 LDA   Oper, X
 LDA   Oper
 LDA   Oper, X
 LDA   Oper, Y
 LDA   (Oper, X)
 LDA   (Oper), Y
    A9
  A5
  B5
  AD
  BD
  B9
  A1
  B1
     2
   2
   2
   3
   3
   3
   2
   2
     2
   3
   4
   4
   4*
   4*
   6
   5*

*  Add 1 if page boundary is crossed.

LDX Load index X with memory

Operation: M → X                                         N Z C I D V
                                                        ✓ ✓ - - - -
                      (Ref: 7.0)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, Y
 Absolute
 Absolute, Y
   LDX # Oper
 LDX   Oper
 LDX   Oper, Y
 LDX   Oper
 LDX   Oper, Y
    A2
  A6
  B6
  AE
  BE
     2
   2
   2
   3
   3
     2
   3
   4
   4
   4*

*  Add 1 when page boundary is crossed.

LDY Load index Y with memory

Operation: M → Y                                         N Z C I D V
                                                        ✓ ✓ - - - -
                      (Ref: 7.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
   LDY # Oper
 LDY   Oper
 LDY   Oper, X
 LDY   Oper
 LDY   Oper, X
    A0
  A4
  B4
  AC
  BC
     2
   2
   2
   3
   3
     2
   3
   4
   4
   4*

*  Add 1 when page boundary is crossed.

LSR Shift right one bit (memory or acemmulator)
               ┌─┬─┬─┬─┬─┬─┬─┬─┐
Operation: 0 ← │7│6│5│4│3│2│1│0│ ← C                     N Z C I D V
               └─┴─┴─┴─┴─┴─┴─┴─┘                        0 ✓ ✓ - - -
                       (Ref: 10.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Accumulator
 Zero Page
 Zero Page, X  
 Absolute
 Absolute, X
   LSR   A
 LSR   Oper
 LSR   Oper, X
 LSR   Oper
 LSR   Oper, X
    4A
  46
  56
  4E
  5E
     1
   2
   2
   3
   3
     2
   5
   6
   6
   7


NOP No operation

Operation: No operation (2 cycles)                       N Z C I D V
                                                         - - - - - -

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   NOP
    EA
     1
     2


ORA "OR" memory with accumulator

Operation: A ∨ M → A                                     N Z C I D V
                                                        ✓ ✓ - - - -
                   (Ref: 2.2.3.1)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   ORA # Oper
 ORA   Oper
 ORA   Oper, X
 ORA   Oper
 ORA   Oper, X
 ORA   Oper, Y
 ORA   (Oper, X)
 ORA   (Oper), Y
    09
  05
  15
  0D
  1D
  19
  01
  11
     2
   2
   2
   3
   3
   3
   2
   2
     2
   3
   4
   4
   4*
   4*
   6
   5

*  Add 1 on page crossing.

PHA Push accumulator on stack

Operation: A ↓                                          N Z C I D V
                                                        - - - - - -
                     (Ref: 8.5)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   PHA
    48
     1
     3


PHP Push accumulator on stack

Operation: P ↓                                          N Z C I D V
                                                        ✓ ✓ - - - -
                     (Ref: 8.11)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   PHP
    08
     1
     3


PLA Pull accumulator from stack

Operation: A ↑                                          N Z C I D V
                                                        ✓ ✓ - - - -
                     (Ref: 8.6)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   PLA
    68
     1
     3


PLP Pull processor status from stack

Operation: P ↑                                          N Z C I D V
                                                         From Stack
                     (Ref: 8.12)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   PLP
    28
     1
     4


ROL Rotate one bit left (memory or accumulator)

             ┌──────────────────────────┐
             │        M or A            │
             ↑ ┌─┬─┬─┬─┬─┬─┬─┬─┐    __  │
Operation:   └─┤7│6│5│4│3│2│1│0│ ← /C/ ←┘               N Z C I D V
               └─┴─┴─┴─┴─┴─┴─┴─┘                        ✓ ✓ ✓ - - -
                   (Ref: 10.3)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Accumulator
 Zero Page
 Zero Page, X  
 Absolute
 Absolute, X
   ROL   A
 ROL   Oper
 ROL   Oper, X
 ROL   Oper
 ROL   Oper, X
    2A
  26
  36
  2E
  3E
     1
   2
   2
   3
   3
     2
   5
   6
   6
   7


ROR Rotate one bit right (memory or accumulator)

             ┌───────────────────────┐
             │ ┌─┐ ┌─┬─┬─┬─┬─┬─┬─┬─┐ │
Operation:   └→│C│→│7│6│5│4│3│2│1│0├─┘                   N Z C I D V
               └─┘ └─┴─┴─┴─┴─┴─┴─┴─┘                     ✓ ✓ ✓ - - -
                   (Ref: 10.4)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Accumulator
 Zero Page
 Zero Page, X  
 Absolute
 Absolute, X
   ROR   A
 ROR   Oper
 ROR   Oper, X
 ROR   Oper
 ROR   Oper, X
    6A
  66
  76
  6E
  7E
     1
   2
   2
   3
   3
     2
   5
   6
   6
   7


Note: ROR instruction will be available on MCS650X microprocessors
after June, 1976.

RTI Return from interrupt

Operation: P↑ PC↑                                        N Z C I D V
                                                         From Stack
                     (Ref: 9.6)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   RTI
    40
     1
     6


RTS Return from subroutine

Operation: PC↑, PC + 1 → PC                              N Z C I D V
                                                         - - - - - -
                     (Ref: 8.2)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   RTS
    60
     1
     6


SBC Subtract memory from accumulator with borrow

Operation: A - M - C → A                                  N Z C I D V
Note: C = Borrow                                         ✓ ✓ ✓ - - ✓
                     (Ref: 2.2.2)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Immediate
 Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   SBC # Oper
 SBC   Oper
 SBC   Oper, X
 SBC   Oper
 SBC   Oper, X
 SBC   Oper, Y
 SBC   (Oper, X)
 SBC   (Oper), Y
    E9
  E5
  F5
  ED
  FD
  F9
  E1
  F1
     2
   2
   2
   3
   3
   3
   2
   2
     2
   3
   4
   4
   4*
   4*
   6
   5*

*  Add 1 when page boundary is crossed.

SEC Set carry flag

Operation: 1 → C                                         N Z C I D V
                                                         - - 1 - - -
                     (Ref: 3.0.1)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   SEC
    38
     1
     2


SED Set decimal mode

Operation: 1 → D                                         N Z C I D V
                                                         - - - - 1 -
                     (Ref: 3.3.1)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   SED
    F8
     1
     2


SEI Set interrupt disable status

Operation: 1 → I                                         N Z C I D V
                                                         - - - 1 - -
                     (Ref: 3.2.1)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   SEI/td>
    78
     1
     2


STA Store accumulator in memory

Operation: A → M                                         N Z C I D V
                                                         - - - - - - 
                     (Ref: 2.1.2)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Zero Page
 Zero Page, X
 Absolute
 Absolute, X
 Absolute, Y
 (Indirect, X)
 (Indirect), Y 
   STA   Oper
 STA   Oper, X
 STA   Oper
 STA   Oper, X
 STA   Oper, Y
 STA   (Oper, X)
 STA   (Oper), Y
    85
  95
  8D
  9D
  99
  81
  91
     2
   2
   3
   3
   3
   2
   2
     3
   4
   4
   5
   5
   6
   6


STX Store index X in memory

Operation: X → M                                         N Z C I D V
                                                         - - - - - - 
                     (Ref: 7.2)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Zero Page
 Zero Page, Y
 Absolute
   STX   Oper
 STX   Oper, Y
 STX   Oper
    86
  96
  8E
     2
   2
   3
     3
   4
   4


STY Store index Y in memory

Operation: Y → M                                         N Z C I D V
                                                         - - - - - - 
                     (Ref: 7.3)

  Addressing
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Zero Page
 Zero Page, X
 Absolute
   STY   Oper
 STY   Oper, Y
 STY   Oper
    84
  94
  8C
     2
   2
   3
     3
   4
   4


TAX Transfer accumulator to index X

Operation: A → X                                         N Z C I D V
                                                         ✓ ✓ - - - -
                     (Ref: 7.11)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   TAX
    AA
     1
     2


TAY Transfer accumulator to index Y

Operation: A → Y                                         N Z C I D V
                                                         ✓ ✓ - - - -
                     (Ref: 7.13)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   TAY
    A8
     1
     2


TYA Transfer index Y to accumulator

Operation: Y → A                                         N Z C I D V
                                                         ✓ ✓ - - - -
                     (Ref: 7.14)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   TYA
    98
     1
     2


TSX Transfer stack pointer to index X

Operation: S → X                                         N Z C I D V
                                                         ✓ ✓ - - - -
                     (Ref: 8.9)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   TSX
    BA
     1
     2


TXA Transfer index X to accumulator

Operation: X → A                                         N Z C I D V
                                                         ✓ ✓ - - - -
                     (Ref: 7.12)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   TXA
    8A
     1
     2


TXS Transfer index X to stack pointer

Operation: X → S                                         N Z C I D V
                                                         - - - - - -
                     (Ref: 8.8)

   Addressing 
Mode  Assembly Language 
Form OP
 CODE No.
 Bytes No.
 Cycles 
   Implied
   TXS
    9A
     1
     2