MCS6500 Programming Manual

MCS6500
Microcomputer Family
Programming Manual


APPENDIX A

INSTRUCTION LIST

ALPHABETIC BY MNEMONIC

DEFINITION OF

INSTRUCTION GROUPS


MCS6501-MCS6505 MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE

    
        ADC Add Memory to Accumulator with Carry JSR Jump to New Location Saving Return Address
        AND "AND" Memory with Accumulator 
        ASL Shift Left One Bit (Memory or Accumulator) LDA Load Accumulator with Memory
        LDX Load Index X with Memory
        BCC Branch on Carry Clear LDY Load Index Y with Memory
        BCS Branch on Carry Set LSR Shift Right One Bit (Memory or Accumulator)
        BEQ Branch on Result Zero 
        BIT Test Bits in Memory with Accumulator NOP No Operation
        BMI Branch on Result Minus 
        BNE Branch on Result not Zero ORA "OR" Memory with Accumulator
        BPL Branch on Result Plus PHA Push Accumulator on Stack
        BRK Force Break PHP Push Processor Status on Stack
        BVC Branch on Overflow Clear PLA Pull Accumulator from Stack
        BVS Branch on Overflow Set PLP Pull Processor Status from Stack
          
        CLC Clear Carry Flag ROL Rotate One Bit Left (Memory or Accumulator)
        CLD Clear Decimal Mode ROR Rotate One Bit Right (Memory or Accumulator)
        CLI Clear Interrupt Disable Bit RTI Return from Interrupt
        CLV Clear Overflow Flag RTS Return from Subroutine
        CMP Compare Memory and Accumulator
        CPX Compare Memory and Index X SBC Subtract Memory from Accumulator with Borrow
        CPY Compare Memory and Index Y SEC Set Carry Flag
        SED Set Decimal Mode
        DEC Decrement Memory by One SEI Set Interrupt Disable Status
        DEX Decrement Index X by One STA Store Accumulator in Memory
        DEY Decrement Index Y by One STX Store Index X in Memory
        STY Store Index Y in Memory
        EOR "Exclusive-Or" Memory with Accumulator 
        TAX Transfer Accumulator to Index X
        INC Increment Memory by One TAY Transfer Accumulator to Index Y
        INX Increment Index X by One TSX Transfer Stack Pointer to Index X
        INY Increment Index Y by One TXA Transfer Index X to Accumulator
        TXS Transfer Index X to Stack Pointer
        JMP Jump to New Location TYA Transfer Index Y to Accumulator
    



A.1 INTRODUCTION

The microprocessor instruction set is divided into three basic groups.
The first group has the greatest addressing flexibility and consists of
the most general purpose instructions such as Load, Add, Store, etc.
The second group includes the Read, Modify, Write instructions such as
Shift, Increment, Decrement and the Register X movement instructions. The
third group contains all the remaining instructions, including all stack
operations, the register Y, compares for X and Y and instructions which do
not fit naturally into Group One or Group Two.
There are eight Group One instructions, eight Group Two instructions,
and all of the 39 remaining instructions are Group Three instructions.
The three groups are obtained by organizing the OP CODE pattern to
give maximum addressing flexibility (16 addressing combinations) to Group
One, to give eight combinations to Group Two instructions and the Group
Three instructions are basically individually decoded.

A.2 GROUP ONE INSTRUCTIONS

These instructions are: Add With Carry (ADC), (AND), Compare (CMP),
Exclusive Or (EOR) , Load A (LDA) , Or (ORA) , Subtract With Carry (SBC) , and
Store A (STA) . Each of these instructions has a potential for 16 addressing
modes. However, in the MCS6501 through MCS6505, only eight of the available
modes have been used.
Addressing modes for Group One are: Immediate, Zero Page, Zero Page
Indexed by X, Absolute, Absolute Indexed by X, Absolute Indexed by Y,
Indexed Indirect, Indirect Indexed. The unused eight addressing modes are
to be used in future versions of the MCS650X product family to allow
addressing of additional on-chip registers, of on-chip I/O ports, and to
allow two byte word processing.

A.3 GROUP TWO INSTRUCTIONS

Group Two instructions are primarily Read, Modify, Write instructions.
There are really two subcategories within the Group Two instructions.
The components of the first group are shift and rotate instructions and
are: Shift Right (LSR) , Shift Left (ASL) , Rotate Left (ROL) , and Rotate
Right (ROR).
The second subgroup includes the Increment (INC) and Decrement (DEC)
instructions and the two index register X instructions, Load X (LDX) and
Store X (STX) . These instructions would normally have eight addressing
modes available to them because of the bit pattern. However, to allow
for upward expansion, only the following addressing modes have been defined:
Zero Page, Zero Page Indexed by X, Absolute, Absolute Indexed
by X, and a special Accumulator (or Register) mode. The four shift instructions
all have register A operations; the incremented or decremented
Load X and Store X instructions also have accumulator modes although the
Increment and Decrement Accumulator has been reserved for other purposes.
Load X from A has been assigned its own mnemonic, TAX. Also included in
this group are the special functions of Decrement X which is one of the
special cases of Store X. Included also in this group in the X decodes
are the TXS and TSX instructions.
All Group One instructions have all addressing modes available to
each instruction. In the case of Group Two instructions, another addressing
mode has been added; that of the accumulator and the other special decodes
have also been implemented in this basic group. However, the primary
function of Group Two instructions is to perform some memory operation using
the appropriate index.
It should be noted for documentation purposes that the X instructions
have a special mode of addressing in which register Y is used for all indexing
operations; thus, instead of Zero Page Indexed by X, X instructions
have Zero Page Indexed by Y, and instead of having Absolute Indexed by X,
X instructions have Absolute Indexed by Y.

A.4 GROUP THREE INSTRUCTIONS

There are really two major classifications of Group Three instructions;
the modify Y register instructions. Load Y (LDY) , Store Y
(STY) , Compare Y (CPY) , and Compare X (CPX) , instructions actually
occupy about half of the OP CODE space for the Group Three instructions.
Increment X (INX) and Increment Y (INY) are special subsets of the Compare X
and Compare Y instructions and all of the branch instructions are in the
Group Three instructions.
Instructions in this group consist of all of the branches: BCC, BCS,
BEQ, BMI, BNE, BPL, BPC and EPS. All of the flag operations are also devoted
to one addressing mode; they are: CLC, SEC, CLD, SED, CLI, SEI and
CLV. All of the push and pull instructions and stack operation instructions
are Group Three instructions. These include: BEK, JSR, PHA, PHP, PLA and
PLP. The JMP and BIT instructions are also included in this group. There
is no common addressing mode available to members of this group. Load Y,
Store Y, BIT, Compare X and Compare Y have Zero Page and Absolute, and all
of the Y and X instructions allow Zero Page Indexed operations and Immediate.