The information in this manual has been reviewed and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. The material in this manual is for informational purposes only and is subject to change without notice.
Second Edition
©MOS TECHNOLOGY, INC. 1976
"All Rights Reserved"
MOS TECHNOLOGY, INC.
950 Rittenhouse Road
Norristown, PA. 19401 Revision A
CHAPTER 1 INTRODUCTORY REMARKS 1.0 Manual Introduction 1.1 Microprocessor Architecture CHAPTER 2 THE DATA BUS, ACCUMULATOR AND ARITHMETIC UNIT 2.0 The Data Bus 2.1 The Accumulator 2.1.1 LDA--Load Accumulator with Memory 2.1.2 STA--Store Accumulator in Memory 2.2 The Arithmetic Unit 2.2.1 ADC--Add Memory with Carry to Accumulator 2.2.1.0 Multiple Precision Addition 2.2.1.1 Signed Arithmetic 2.2.1.2 Decimal Audition 2.2.1.3 Add Summary 2.2.2 SBC--Subtract Memory from Accumulator with Borrow 2.2.2.0 Multiple Precision Subtraction 2.2.2.1 Signed Arithmetic 2.2.2.2 Decimal Subtract 2.2.3 Carry and Overflow During Arithmetic Operations 2.2.4 Logical Operands 2.2.4.1 AND--"AND" Memory with Accumulator 2.2.4.2 ORA--"OR" Memory with Accumulator 2.2.4.3 EOR--"Exclusive OR" Memory with Accumulator CHAPTER 3 CONCEPTS OF FLAGS AND STATUS REGISTER 3.0 Carry Flag (C) 3.0.1 SEC—Set Carry Flag 3.0.2 CLC—Clear Carry Flag 3.1 Zero Flag (Z) 3.2 Interrupt Disable (I) 3.2.1 SEI—Set Interrupt Disable 3.2.2 CLI—Clear Interrupt Disable 3.3 Decimal Mode Flag (D) 3.3.1 SED-Set Decimal Mode 3.3.2 CLD—Clear Decimal Mode 3.4 Break Command (B) 3.5 Expansion Bit 3.6 Overflow (V) 3.6.1 CLV—Clear Overflow Flag 3.6.2 Determination of Overflow 3.7 Negative Flag (N) 3.8 Flag Summary CHAPTER 4 TEST, BRANCH AND JUMP INSTRUCTIONS 4.0 Concepts of Program Sequence 4.0.1 Use of Program Counter to Fetch an Instruction 4.0.2 JMP—Jump to New Location 4.1 Branching 4.1.1 Basic Concept of Relative Addressing 4.1.2 Branch Instructions 4.1.2.1 BMI-Branch on Result Minus 4.1.2.2 BPL—Branch on Result Plus 4.1.2.3 BCC—Branch on Carry Clear 4.l.2.4 BCS-Branch on Carry Set 4.1.2.5 BEQ—Branch on Result Zero 4.1.2.6 BNE—Branch on Result Not Zero 4.1.2.7 BVS—Branch on Overflow Set 4.1.2.8 BVC-Branch on Overflow Clear 4.1.3 Branch Summary 4.1.4 Solution to Branch Out of Range 4.2 Test Instructions 4.2.1 CMP—Compare Memory and Accumulator 4.2.2 Bit Testing 4.2.2.1 BIT—Test Bits in Memory with Accumulator CHAPTER 5 NON-INDEXING ADDRESSING TECHNIQUES 5.0 Addressing Techniques 5.1 Concepts of Pipelining and Program Sequence 5.2 Memory Utilization 5.2.1 I/O Control 5.2.2 Memory Allocation 5.3 Implied Addressing 5.4 Immediate Addressing 5.5 Absolute Addressing 5.6 Zero Page Addressing 5.7 Relative Addressing CHAPTER 6 INDEX REGISTERS AND INDEX ADDRESSING CONCEPTS 6.0 General Concept of Indexing 6.1 Absolute Indexed 6.2 Zero Page Indexed 6.3 Indirect Addressing 6.4 Indexed Indirect Addressing 6.5 Indirect Indexed Addressing 6.6 Indirect Absolute 6.7 Application of Indexes CHAPTER 7 INDEX REGISTER INSTRUCTIONS 7.0 LDX—Load Index Register X from Memory 7.1 LDY—Load Index Register Y from Memory 7.2 STX—Store Index Register X in Memory 7.3 STY—Store Index Register Y in Memory 7.4 INX—Increment Index Register X by One 7.5 INY—Increment Index Register Y by One 7.6 DEX—Decrement Index Register X by One 7.7 DEY—Decrement Index Register Y by One 7.8 CPX—Compare Index Register X to Memory 7.9 CPY—Compare Index Register Y to Memory 7.10 Transfers Between the Index Registers and Accumulator 7.11 TAX—Transfer Accumulator to Index X 7.12 TXA—Transfer Index X to Accumulator 7.13 TAY—Transfer Accumulator to Index Y 7.14 TYA-Transfer Index Y to Accumulator 7.15 Summary of Index Register Applications and Manipulations CHAPTER 8 STACK PROCESSING 8.0 Introduction to Stack and to Push Down Stack Concept 8.1 JSR—Jump to Subroutine 8.2 RTS—Return from Subroutine 8.3 Implementation of Stack in MCS6501 Through MCS6505 8.3.1 Summary of Stack Implementation 8.4 Use of the Stack by the Programmer 8.5 PHA—Push Accumulator on Stack 8.6 PLA—Pull Accumulator from Stack 8.7 Use of Pushes and Pulls to Communicate Variables Between Subroutine Operations 8.8 TXS—Transfer Index X to Stack Pointer 8.9 TSX—Transfer Stack Pointer to Index X 8.10 Saving of the Processor Status Pointer 8.11 PHP—Push Processor Status on Stack 8.12 PLP—Pull Processor Status from Stack 8.13 Summary on the Stack CHAPTER 9 RESET AND INTERRUPT CONSIDERATIONS 9.0 Vectors 9.1 Reset or Restart 9.2 Start Function 9.3 Programmer Considerations for Initialization Sequences 9.4 Restart 9.5 Interrupt Considerations 9.6 RTI—Return from Interrupt 9.7 Software Polling for Interrupt Causes 9.8 Fully Vectored Interrupts 9.8.1 JMP Indirect 9.9 Interrupt Summary 9.10 Non-Maskable Interrupt 9.11 BRK—Break Command 9.12 Memory Map CHAPTER 10 SHIFT AND MEMORY MODIFY INSTRUCTIONS 10.0 Definition of Shift and Rotate 10.1 LSR—Logical Shift Right 10.2 ASL—Arithmetic Shift Left 10.3 ROL—Rotate Left 10.4 ROR—Rotate Right 10.5 Accumulator Mode Addressing 10.6 Read/Modify/Write Instructions 10.7 INC—Increment Memory by One 10.8 DEC—Decrement Memory by One 10.9 General Note on Read/Modify/Write Instructions CHAPTER 11 PERIPHERAL PROGRAMMING 11.0 Review of MCS6520 for I/O Operations 11.1 MCS6520 Interrupt Control 11.2 Implementation Tricks for Use of the MCS6520 Peripheral Interface Devices 11.2.1 Shortcut Polling Sequences 11.2.2 Bit Organization on MCS6520s 11.2.3 Use of READ/MODIFY/WRITE Instruction for Keyboard Encoding 11.3 MCS6530 Programming 11.3.1 Reading of the Counter Register 11.4 How to Organize to Implement Coding 11.4.1 Label Standards 11.5 Comprehensive I/O Program APPENDICES A. Instruction List, Alphabetic by Mnemonic, Definition of Instruction Groups MCS6501 - MCS6505 Microprocessor Instruction Set —- Alphabetic Sequence A.1 Introduction A.2 Group One Instructions A.3 Group Two Instructions A.4 Group Three Instructions B. Instruction List, Alphabetic by Mnemonic, with OP CODEs, Execution Cycles and Memory Requirements C. Instruction Addressing Modes and Related Execution Times D. Operation Code Instruction Listing Hexadecimal Sequence E. Summary of Addressing Modes E.1 Implied Addressing E.2 Immediate Addressing E.3 Absolute Addressing E.4 Zero Page Addressing E.5 Relative Addressing E.6 Absolute Indexed Addressing E.7 Zero Page Indexed Addressing E.8 Indexed Indirect Addressing E.9 Indirect Indexed Addressing F. MCS650X Programming Model G. Discussion—Indirect Addressing H. Review of Binary and Binary Coded Decimal Arithmetic LIST OF EXAMPLES CHAPTER 2 THE DATA BUS, ACCUMULATOR AND ARITHMETIC UNIT 2.1 Add 2 Numbers with Carry; No Carry Generation 2.2 Add 2 Numbers with Carry; Carry Generation 2.3 Adding Two 16-Bit Numbers 2.4 Add Two 16-Bit Numbers, No Carry from Low Order Add 2.5 Add Two 16-Bit Numbers, with Carry from Low Order Add 2.6 Add 2 Positive Numbers with No Overflow 2.7 Add 2 Positive Numbers with Overflow 2.8 Add Positive and Negative Number with Positive Result 2.9 Add Positive and Negative Number with Negative Result 2.10 Add 2 Negative Numbers without Overflow 2.11 Add 2 Negative Numbers with Overflow 2.12 Decimal Addition 2.13 Subtract 2 Numbers with Borrow; Positive Result 2.14 Subtract 2 Numbers with Borrow; Negative Result 2.15 Subtracting Two 16-Bit Numbers 2.16 Subtract in Double Precision Format; Positive Result 2.17 Subtract in Double Precision Format; Negative Result 2.18 Decimal Subtraction 2.19 Clearing a Bit with "AND" 2.20 Setting a Bit with "OR" 2.21 Complementing a Byte with "EOR" CHAPTER 4 TEST, BRANCH AND JUMP INSTRUCTIONS 4.1 Accessing Instructions with the P-Counter Value 4.2 Accessing Data Addressing with P-Counter Value 4.3 Use of JMP Instruction 4.4 Illustration of "Branch on Carry Set" 4.5 Sequencing Two Branch Instructions 4.6 Use of JMP to Branch Out of Range 4.7 Using the CMP Instruction 4.8 Sample Program Using the BIT Test CHAPTER 5 NON-INDEXING ADDRESSING TECHNIQUES 5.1 Using Absolute Addressing 5.2 Demonstration of "Pipelining" Effect 5.3 Illustration of Implied Addressing 5.4 Illustration of Immediate Addressing 5.5 Illustration of Absolute Addressing 5.6 Illustration of Zero Page Addressing 5.7 Illustration of Relative Addressing; Branch Not Take 5.8 Illustration of Relative Addressing; Branch Positive Taken, No Crossing of Page Boundaries 5.9 Illustration of Relative Addressing; Branch Negative Taken, Crossing of Page Boundaries CHAPTER 6 INDEX REGISTERS AND INDEX ADDRESSING CONCEPTS 6.1 Moving Five Bytes of Data with Straight Line Code 6.2 Moving Five Bytes of Data with Loop 6.3 Coded Detail of Moving Fields with Loop 6.4 Moving Five Bytes of Data with Index Register 6.5 Moving Five Bytes of Data by Decrementing the Index Register 6.6 Absolute Indexed; with No Page Crossing 6.7 Absolute Indexed; with Page Crossing 6.8 Illustration of Zero Page Indexing 6.9 Demonstrating the Wrap-Around 6.10 Illustration of Indexed Indirect Addressing 6.11 Indirect Indexed Addressing (No Page Crossing) 6.12 Indirect Indexed Addressing (with Page Crossing) 6.13 Absolute Indexed Add—Sample Program 6.14 Indexed Indirect Add—Sample Program 6.15 Move N Bytes (N < 256) 6.16 Move N Bytes (N > 256) CHAPTER 8 STACK PROCESSING 8.1 Basic Stack Map for 3-Deep JMP to Subroutine 8.2 Basic Stack Operation 8.3 Illustration of JSR Instruction 8.4 Illustration of RTS Instruction 8.5 Memory Map for RTS Instruction 8.6 Expansion of RTS Memory Map 8.7 Call-a-Move Subroutine Using Preassigned Memory Locations 8.8 Operation of PHA, Assuming Stack at 0lFF 8.9 Operation of PLA, Stack from Example 8.8 8.10 Call-a-Move Subroutine Using the Stack to Communicate 8.11 Jump to subroutine (JSR) Followed by Parameters CHAPTER 9 RESET AND INTERRUPT CONSIDERATIONS 9.1 Illustration of Start Cycle 9.2 Interrupt Sequence 9.3 Return from Interrupt 9.4 Illustration of Save and Restore for Interrupts 9.5 Interrupt Polling 9.6 Illustration of JMP Indirect 9.7 Break-Interrupt Processing 9.8 Patching with a Break Utilizing PROMs CHAPTER 10 SHIFT AND MEMORY MODIFY INSTRUCTIONS 10.1 General Shift and Rotate 10.2 Rotate Accumulator Left 10.3 Rotate Memory Left Absolute,X 10.4 Move a New BCD Number into Field CHAPTER 11 PERIPHERAL PROGRAMMING 11.1 The MCS6520 Register Map 11.2 General PIA Initialization 11.3 Interrupt Mode Setup 11.4 CA2; CB2 Output Control 11.5 Routine to Change CB1 or CB2 Using Bit 3 Control 11.6 Polling the MCS6520 11.7 Coding for Strobing an 8 x 8 Keyboard 11.8 Polling for Active Signal LIST OF FIGURES CHAPTER 2 THE DATA BUS, ACCUMULATOR AND ARITHMETIC UNIT 2.1 Partial Block Diagram of MCS650X 2.2 Partial Block Diagram Including Arithmetic Logic Unit of MCS650X 2.3 Byte Orientation with Sign Position CHAPTER 3 CONCEPTS OF FLAGS AND STATUS REGISTER 3.1 Partial Block Diagram of MCS650X Including P-Register 3.2 Processor Status Register, "P" CHAPTER 4 TEST, BRANCH AND JUMP INSTRUCTIONS 4.1 Partial Block Diagram of MCS650X Including Program Counter and Internal Address Bus 4.2 Use of Conditional Test CHAPTER 5 NON-INDEXING ADDRESSING TECHNIQUES 5.1 Address Bus and Relation to Memory Field 5.2 Example of Timing—MCS650X Family CHAPTER 6 INDEX REGISTERS AND INDEX ADDRESSING CONCEPTS 6.1 Moving Five Bytes of Data with Loop 6.2 Moving Five Bytes of Data with Counter 6.3 Partial Block Diagram of MCS650X Including Index Register 6.4 Indirect Addressing—Pictorial Drawing 6.5 Indexed Indirect Addressing 6.6 Indirect Indexed Addressing CHAPTER 8 STACK PROCESSING 8.1 Partial Block Diagram of MCS650X Including Stack Pointer, S CHAPTER 10 SHIFT AND MEMORY MODIFY INSTRUCTIONS 10.1 Flow Chart for Moving in a New BCD Number CHAPTER 11 PERIPHERAL PROGRAMMING 11.1 Keyboard Encoding Matrix Program 11.2 Keyboard Strobe Sequence 11.3 Program Flow-Polling for Active Signal
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